Throughput Analysis of the Bifurcated Input-Queued ATM Switch

In this paper there suggested is a bifurcated (or multiple) input-queued ATM switch in which a buffer for each input port is divided into multiple (m) buffer blocks, i.e., bifurcated buffers, for enhancement of the limited throughput of the ordinary input-queued switch using a single FIFO. As the contention/arbitration rule for the bifurcated input-queued switching scheme, free and restricted contention rules are come up with and discussed. The free rule allows an input port to switch up to m cells at the cost of internal speedup. With the restricted rule, on the other hand, an input port can switch no more than one cell in a time slot so that the switch operates at the same speed as the external link speed. The throughput bound for the bifurcated input-queued switch is analyzed for both rules through the generalization of the analysis by Karol et al. [1]. The throughput bound approaches to 1.0 as m becomes large enough, irrespective of the contention/arbitration rule. key words: bifurcated input-queued ATM switch